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 IS62U6416LL
IS62U6416LL
64K x 16 LOW VOLTAGE, ULTRA-LOW POWER CMOS STATIC RAM
ISSI
DESCRIPTION
(R) ISSI
(R)
ADVANCE INFORMATION DECEMBER 1998
1 2 3 4 5 6
FEATURES
* Access time: 200 ns * CMOS low power operation - 40 mW (typical) operating - 90 W (typical) standby * TTL compatible interface levels * Single 1.8V-2.7V power supply * Fully static operation: no clock or refresh required * Three state outputs * Data control for upper and lower bytes * Industrial temperature available * Available in Jedec Std 44-pin SOJ package, 44-pin TSOP (Type II), and 48-pin mini BGA
The ISSI IS62U6416LL is an ultra-low power, 1,048,576-bit static RAM organized as 65,536 words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques yields access times as fast as 200 ns with low power consumption. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access.
FUNCTIONAL BLOCK DIAGRAM
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A0-A15 DECODER 64K x 16 MEMORY ARRAY
8 9
VCC GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT
COLUMN I/O
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CE OE WE UB LB
The specification contains ADVANCE INFORMATION. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 1998, Integrated Silicon Solution, Inc.
CONTROL CIRCUIT
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Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION SR034-0C
12/09/98
1
IS62U6416LL
PIN CONFIGURATIONS 44-Pin SOJ
A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC
ISSI
44-Pin TSOP
A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC
(R)
48-Pin mini BGA (Top View)
1 2 3 4 5 6
PIN DESCRIPTIONS
A0-A15 I/O0-I/O15 Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground
A B C D E F G H
LB I/O 8 I/O 9 GND Vcc I/O 14 I/O 15 NC
OE UB I/O 10 I/O 11 I/O 12 I/O 13 NC A8
A0 A3 A5 NC NC A14 A12 A9
A1 A4 A6 A7 NC A15 A13 A10
A2 CE I/O 1 I/O 3 I/O 4 I/O 5 WE A11
N/C I/O 0 I/O 2 Vcc GND I/O 6 I/O 7 NC
CE OE WE LB UB
NC Vcc GND
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION SR034-0C
12/09/98
IS62U6416LL
ISSI
(R)
TRUTH TABLE
Mode Not Selected Output Disabled Read
WE
X H X H H H L L L
CE
H L L L L L L L L
OE
X H X L L L X X X
LB
X X H L H L L H L
UB
X X H H L L H L L
I/O Pin I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN
Vcc Current ISB1, ISB2 ICC ICC
1 2 3 4
Write
ICC
AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0.4 to 1.8V(1) 5 ns 0.9V(1) See Figures 1 and 2
5 6 7
3070 1.8V
AC TEST LOADS
3070 1.8V OUTPUT 100 pF Including jig and scope 3150
THEVENIN EQUIVALENT 1554 OUTPUT 0.91V
8 9
OUTPUT 30 pF Including jig and scope 3150
Figure 3.
Figure 1.
Figure 2.
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Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION SR034-0C
12/09/98
3
IS62U6416LL
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Storage Temperature Power Dissipation DC Output Current (LOW) Value -0.5 to Vcc +0.5 -65 to +150 1.5 20 Unit V C W mA
ISSI
(R)
Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 1.8V (Min.) to 2.7V (Max.) 1.8V (Min.) to 2.7V (Max.)
DC ELECTRICAL CHARACTERISTICS (Over Operating Range Unless Otherwise Specified)
Symbol VOH VOL VIH VIL(1) ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage GND VIN VCC GND VOUT VCC, Outputs Disabled Test Conditions VCC = Min., IOH = -0.44 mA VCC = Min., IOL = 0.33 mA Min. 1.6 -- 1.6 -0.2 -1 -1 Max. -- 0.4 VCC + 0.2 0.4 1 1 Unit V V V V A A
Note: 1. VIL (min.) = -1.5V for pulse width less than 30 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range Unless Otherwise Specified)
Symbol ICC Parameter Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., IOUT = 0 mA, f = fMAX CE = VIH VCC = Max., VIN = VIH or VIL CE VIH , f = 0 Com. Ind. Com. Ind. Com. Ind. -200 Min. Max. -- -- -- -- -- -- 25 40 0.3 0.3 5 5 Unit mA
ISB1
mA
ISB2
CE VCC - 0.2V,
VIN 0.2V, f = 0
VCC = Max.,
A
Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency; f = 0 means no input lines change.
4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION SR034-0C
12/09/98
IS62U6416LL
ISSI
(R)
CAPACITANCE(1)
Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 8 10 Unit pF pF
1 2 3 4
Note: 1. Tested initially and after any design or process changes that may affect these parameters.
READ CYCLE SWITCHING CHARACTERISTICS(1)
(Over Operating Range) -200 Min. Max. 200 -- 20 -- -- 0 20 0 30 -- 0 20 -- 200 -- 200 100 50 -- 50 -- 100 50 --
5
Unit ns ns ns ns ns ns ns ns ns ns ns ns
Symbol
Parameter Read Cycle Time Address Access Time Output Hold Time
tRC tAA tOHA tACE tDOE tHZOE(2) tLZOE(2) tHZCE tBA tHZB tLZB
(2)
6 7 8 9
tLZCE(2)
CE Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output
Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4 to 1.8V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500mV from steady-state voltage. Not 100% tested.
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Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION SR034-0C
12/09/98
5
IS62U6416LL
AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
tRC
ISSI
(R)
ADDRESS
tAA tOHA tOHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ CYCLE NO. 2(1,3)
tRC
ADDRESS
tAA tOHA
OE
tDOE tHZOE
CE
tLZCE
tLZOE tACE tHZCE
LB, UB
tBA tHZB
DATA VALID
DOUT
HIGH-Z
tLZB
Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition.
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Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION SR034-0C
12/09/98
IS62U6416LL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol Parameter Write Cycle Time -200 Min. Max. 200 160 160 0 0 160 160 160 0 -- 20 -- -- -- -- -- -- -- -- -- 50 -- Unit ns ns ns ns ns ns ns ns ns ns ns
ISSI
(R)
tWC tSCE tAW tHA tSA tPWB tPWE tSD tHD tHZWE
(3)
1 2 3 4 5 6 7
Min. Max. Unit
CE to Write End
Address Setup Time to Write End Address Hold from Write End Address Setup Time
LB, UB Valid to End of Write WE Pulse Width
Data Setup to Write End Data Hold from Write End
tLZWE(3)
WE LOW to High-Z Output WE HIGH to Low-Z Output
Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4V to 1.8V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage.
DATA RETENTION CHARACTERISTICS
Symbol Parameter Test Condition
VDR IDR tSDR tRDR
Vcc for Data Retention Data Retention Current Data Retention Set up Time Recovery Time
CE VCC - 0.2V
VCC = VDR CE VCC - 0.2V See Data Retention Waveform See Data Retention Waveform
1.5 -- 0 tRC
-- 5.0 -- --
V A ns ns
8 9
DATA RETENTION TIMING DIAGRAM
tSDR VCC 1.8V
DATA RETENTION MODE
10
tRDR
11
VIH VDR CE GND CE VCC - 0.2V
12
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION SR034-0C
12/09/98
7
IS62U6416LL
AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (WE Controlled)
tWC
ISSI
(R)
ADDRESS
tSCE tHA
CE
tPWB
LB, UB
tAW tPWE
WE
tSA
WRITE(1)
tSD tHD
DIN
tHZWE tLZWE
UNDEFINED HIGH-Z UNDEFINED HIGH-Z
DOUT
Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE).
8
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION SR034-0C
12/09/98
IS62U6416LL
ORDERING INFORMATION Commercial Range: 0C to +70C
Speed (ns) Order Part No. 200 IS62U6416LL-20T IS62U6416LL-20K IS62U6416LL-20B Package Plastic TSOP (Type II) 400-mil Plastic SOJ Mini BGA (6mm x 8mm)
ISSI
(R)
1 2 3 4 5
ORDERING INFORMATION Industrial Range: -40C to +85C
Speed (ns) Order Part No. 200 IS62U6416LL-20TI IS62U6416LL-20KI IS62U6416LL-20BI Package Plastic TSOP (Type II) 400-mil Plastic SOJ Mini BGA (6mm x 8mm)
NOTICE Integrated Silicon Solution, Inc., reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. Integrated Silicon Solution, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user's specific application. While the information in this publication has been carefully checked, Integrated Silicon Solution, Inc. shall not be liable for any damages arising as a result of any error or omission. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of Integrated Silicon Solution, Inc. is adequately protected under the circumstances. Copyright 1998 Integrated Silicon Solution, Inc. Reproduction in whole or in part, without the prior written consent of Integrated Silicon Solution, Inc., is prohibited.
6 7 8 9
10
ISSI
(R)
Integrated Silicon Solution, Inc.
2231 Lawson Lane Santa Clara, CA 95054 Fax: (408) 588-0806 Toll Free: 1-800-379-4774 email: sales@issi.com http://www.issi.com
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION SR034-0C
12/09/98
11
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